In semiconductor processing, it is often necessary to provide electrical connections between different levels of interconnect layers. The interconnect layers are separated by a interlevel insulation layer, typically an oxide layer. Holes or "vias" are formed through the interlevel insulation layer, and a conducting material is deposited in the via. Thereafter, the second level of interconnect is formed over the interlevel insulation layer and the via.
For a 1.5 micrometer (or less) via, a via slope, measured from the horizontal, of 50.degree. or less is necessary to achieve a 50% step coverage of the metal layers. Less coverage would compromise the integrity of the device.
In the prior art, two methods have been used to form the sloped via. In the first method, a photoresist layer is used to define the vias through the interlevel insulation layer. A hard bake is used to flow the resist, thus causing the resist thickness to increase with distance from the via pattern. During the etch phase, the resist at the edge of the via will be thin enough that the etchant will eventually remove the resist and etch. Thus, a sloped via is formed. A second method of forming a sloped via uses a resist-attacking additive in the oxide etch gas to increase the size of the pattern as the via is etched.
Both of the aforementioned methods of forming a sloped via suffer from numerous problems. First, both methods are difficult to control. Second, the via slope is limited to about 60.degree. using these methods, which is insufficient to provide reliable step coverage.
A more modern technique involves using CVD (chemical vapor deposition) tungsten in non-sloped vias through a planar interlevel insulation layer. While this method provides reliable contacts between interconnect layers, the machinery to perform this method costs in excess of one million dollars in many applications.
Therefore, a need has arisen in the industry to provide a sloped via, having an angle of 50.degree. or less, at a reasonable cost.